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Partcl

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Partcl

Design a chip in minutes

partcl.com
B2B

Company research

Public company, workplace, funding, and market signals

Updated Jul 29, 2026

Overview

Partcl is a San Francisco-based, YC-backed startup building GPU-accelerated EDA tools for chip design. Its public products focus on RTL optimization, physical-design acceleration, and a high-performance design database, with the goal of cutting chip-design feedback from hours/days to seconds/minutes.

Primary product

GPU-accelerated EDA platform for chip design optimization (RTL Super Optimization, Boson, and Nucleus)

Founded

2025

Headquarters

San Francisco, California, United States

Team size

1-10

Industry

Technology, Information and Internet

Sub-industry

Electronic Design Automation (EDA) / semiconductor software

Offices

San Francisco, California, United States (HQ)

Business model

B2B software
developer tools

Funding

Stage

Seed

Latest round

Seed · Apr 2026

Latest amount

$5M

Seed

Apr 2026 · Khosla Ventures

$5M

Pre-Seed

May 2025 · Y Combinator

People & investors

Leadership

William Salcedo

Founder & CEO

Vamshi Balanaga

Founder & CTO

Investors

468 Capital
Founders Capital
Khosla Ventures
Liquid 2 Ventures
Paul Graham
Pioneer Fund
Tekedia Capital
Transpose Platform
Y Combinator

Work & culture

Small, highly technical, research-heavy startup culture centered on hard optimization and systems problems. Public activity suggests a bias toward open technical challenges, rapid iteration, and community engagement in chip-design research.

Compensation

Public SF job posts list $130K-$300K base salary ranges. The Backend EDA Compiler Engineer role advertises 0.10%-1.00% equity, and the Founding Engineer (Systems + ML) role advertises 0.50%-2.00% equity. Both roles are open to new grads.

Product & market

Differentiators

  • —GPU-native acceleration
  • —physics-informed models
  • —700x-1000x faster feedback claims than legacy tools
  • —end-to-end flow from RTL optimization through physical design
  • —seconds/minutes instead of hours/days

Technology

Python
Apache
LLVM
SystemVerilog
Verilog
GitHub
PyTorch
CUDA
C

Customers

chip designers
ASIC physical-design teams
AI accelerator teams
embedded/IoT teams
mobile SoC teams

Competitors

Cadence
Synopsys
Siemens EDA
OpenROAD / open-source EDA tooling

Scale & contact

Estimated monthly visits

8.4K

Traffic estimate as of Jul 2026

contact@partcl.com

Latest news

Partcl × Hudson River Trading Macro Placement Challenge Winners

LinkedIn · Jul 2026

Partcl announced the winners of its macro placement challenge with Hudson River Trading, saying the competition drew 223 registrations and 132 verified eligible submissions.

How team Archgen Ranked First in the HRT and Partcl Macro Placement Challenge

Substack · Jun 2026

A technical write-up of the winning approach for the challenge; it discusses the benchmark setup, proxy cost scoring, and the verified rank-1 result.

Partcl raises $5M led by Khosla Ventures

LinkedIn · Apr 2026

Founder/CEO William Salcedo announced that Partcl raised $5M led by Khosla Ventures, with participation from several investors including 468 Capital, Liquid 2 Ventures, Transpose Platform, Pioneer Fund, Tekedia Capital, Founders Capital, Paul Graham, and Y Combinator.

Partcl and Hudson River Trading launch macro placement challenge

LinkedIn · Mar 2026

Partcl announced an open competition with Hudson River Trading to build better macro placement algorithms, with prizes and a public benchmark-driven evaluation process.

Partcl Launches: Design Chips in Minutes

Fondo · Feb 2026

Launch coverage describing Partcl’s GPU-accelerated EDA approach, founders, product claims, and target use cases for AI accelerators, embedded/IoT, and mobile SoCs.

APIBlogBosonGitHub orgHomepageLinkedIn companyNucleusRTL Super OptimizationYC company pageYC jobs
SourcesOfficial homepageYC company pageYC jobsLinkedIn company pageGitHub organizationFounder/CEO LinkedInFounder/CTO LinkedInPartcl/HRT challenge repoLaunch articleFunding announcement

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