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atopile

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atopile

We make tools to design electronics circuit boards with code

atopile.io
HQ: San Francisco, CA, USA
1-10
B2B

Company research

Public company, workplace, funding, and market signals

Updated Jul 30, 2026

Overview

atopile is a San Francisco-based, YC Winter 2024, open-core electronics design automation company that lets hardware teams design circuit boards in code, then validate and ship them with simulation, CI-style checks, and integrations into existing EDA tools.

Primary product

A code-native EDA platform plus the .ato language/compiler/toolchain for designing electronic circuit boards with code.

Founded

2023

Headquarters

San Francisco, California, United States

Team size

1-10

Industry

Software Development

Sub-industry

Electronics Design Automation (EDA) / PCB design software

Offices

San Francisco, California, United States

Business model

open-core
B2B SaaS
enterprise software

Funding

Stage

pre-seed / early-stage VC

Total raised

$625K

Latest round

Pre-Seed / Convertible Note · Apr 2024

Latest amount

$500K

Pre-Seed / Convertible Note

Apr 2024 · Y Combinator

$500K

Seed

Mar 2024

$125K

People & investors

Leadership

Narayan Powderly

Co-CEO

Ioannis Papamanoglou

Co-founder & Chief Technology Officer

David Battisti

Head of Sales

Founders

Matt Wildoer

Co-founder; former CEO

Timothée Peter

Co-founder

Investors

Lombardstreet Ventures
Offline Ventures
SurgePoint Capital
Tarek Alaruri
Y Combinator

Work & culture

Builder-oriented and high-agency, with an emphasis on deep technical expertise, end-to-end ownership, transparency, and open-source/open-core workflows.

Compensation

The clearest public compensation signal found was a Member of Technical Staff posting in San Francisco at $180K-$300K salary plus 0.10%-1.00% equity; no broader compensation policy was publicly stated.

Product & market

Pricing

Open-core with free/open-source core tooling and sales-led enterprise features for larger deployments.

Differentiators

  • —Code-first rather than GUI-first hardware design
  • —Open-core and MIT-licensed .ato language/compiler
  • —Single source of truth spanning design, sourcing, firmware, verification, and manufacturing
  • —CLI, Python API, and MCP server automation
  • —Agent-friendly workflow with reviewable diffs and continuous validation
  • —Works with existing layout tools such as Altium today, with more CAD integrations planned

Technology

Python
KiCad
VS Code
Cursor
debugpy
GitHub
GitLab
CI/CD
SPICE
MCP server

Customers

hardware engineering teams
electronics / PCB design teams
firmware teams
sourcing / procurement teams
manufacturing and verification teams

Competitors

Altium Designer
Cadence Allegro
Mentor Expedition
KiCad
other PCB / EDA design tools

Scale & contact

Estimated revenue

≈$1.1M estimated ARR

Estimated monthly visits

1.9K

Traffic estimate as of Jun 2026

info@atopile.io

Latest news

Code-Based PCB Design with AI: Inside atopile

Altium Academy / Podbean · Jun 2026

Podcast interview with Narayan Powderly and Ioannis Papamanoglou on atopile’s code-first, AI-driven PCB design approach, its integration with Altium Designer, and the roadmap around supply chain and firmware integration.

atopile launches a new language to design electronic circuit boards with code

Fondo · Feb 2026

Coverage of atopile’s launch and positioning as an open-core, code-based electronics design platform with GitHub and docs links.

Atopile Faces User Criticism Over Lack of Real Circuit Examples and Limited Component Library

BigGo News · Jul 2025

Community criticism focused on missing practical examples and a limited component library; also noted that KiCad is still required for PCB layout/routing.

atopile just went live on Launch YC!

LinkedIn post by Timothée Peter · Mar 2024

Launch announcement describing atopile as a programming language and toolchain to automate hardware design and emphasizing software-style workflows for electronics.

Atopile Wants You To Code Schematics

Hackaday · Feb 2024

Early third-party coverage of atopile’s code-first approach to schematics, noting benefits for reuse and maintainability as well as tradeoffs versus traditional schematic workflows.

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